Author :
Gilbert, P. ; Yang, I. ; Pettinato, C. ; Angyal, M. ; Boeck, B. ; Fu, C. ; VanGompel, T. ; Tiwari, R. ; Sparks, T. ; Clark, W. ; Dang, C. ; Mendonca, J. ; Chu, B. ; Lucas, K. ; Kling, M. ; Roman, B. ; Park, E. ; Huang, F. ; Woods, M. ; Rose, D. ; McGuffin
Author_Institution :
Networking & Comput. Syst. Group, Motorola Inc., Austin, TX, USA
Abstract :
A high performance 0.10 /spl mu/m gate length CMOS technology has been developed with six levels of scaled copper interconnects. Transistors of 0.10 /spl mu/m-0.13 /spl mu/m gate length with physical 3 nm gate oxides and 0.175 /spl mu/m local interconnect features are optimized for 1.5 V operation to achieve 15 ps unloaded ring oscillator delay. Complementary phase shift masks for superior gate control and low-K dielectrics for reduced coupling capacitance enable an aggressive (>15%) linear shrink of the previous generation copper-based technology. Critical technology layer pitches enable fabrication of 4.5 /spl mu/m/sup 2/ 6T-SRAM cells.
Keywords :
CMOS integrated circuits; SRAM chips; copper; digital integrated circuits; integrated circuit interconnections; integrated circuit metallisation; phase shifting masks; 0.1 to 0.13 micron; 1.5 V; 2 nm; 6T-SRAM cells; Cu; SRAM cell fabrication; complementary phase shift masks; coupling capacitance reduction; deep submicron CMOS technology; gate control; low-K dielectrics; scaled Cu metallization; scaled copper interconnects; static RAM cells; CMOS technology; Computer networks; Copper; Delay; Fabrication; Isolation technology; MOS devices; Metallization; Ring oscillators; Threshold voltage;
