Rapid and high-level constraint-driven prototyping using lab VIEW FPGA

Many varied domain experts use Lab VIEW as a graphical system design tool to implement DSP algorithms on myriad target architectures. In this paper, we introduce the latest LabVIEW FPGA compiler that enables domain experts with minimum hardware knowledge to quickly implement, deploy, and verify their domain-specific applications on FPGA hardware. We present two compiler techniques that we use to 1) extract extra parallelism from a user´s application to take advantage of the parallel hardware resources of the FPGA and 2) minimize memory-access traffic, which is often a bottleneck that restricts overall FPGA performance. Finally, our approach provides the user a simple constraint-driven experience to maximize their development efficiency. We use two case studies in two different domains, a 3GPP Turbo decoder and a Smith-Waterman algorithm, to show the benefits our tool provides to users.