DocumentCode :
257638
Title :
Symbolic verification of requirements in VRS system
Author :
Letychevskyi, Oleksandr ; Weigert, T.
Author_Institution :
Glushkov Inst. of Cybern., Kiev, Ukraine
fYear :
2014
fDate :
25-29 Aug. 2014
Firstpage :
331
Lastpage :
332
Abstract :
VRS (Verification Requirements Specifications) system is a tool for processing formal requirements during the initial stage of software, hardware, or system development. Symbolic modeling and deductive methods are used for detection of issues such as safety violations, deadlocks, nondeterminism, or livelocks. The formal representation of requirements also supports the generation of test suites as well as the synthesis of a design model.
Keywords :
formal verification; program testing; symbol manipulation; VRS system; deadlocks; deductive methods; design model synthesis; formal requirements; formal requirements representation; hardware development; livelocks; nondeterminism; safety violations; software development; symbolic modeling; symbolic requirements verification; system development; test suites; verification requirements specifications; Abstracts; Cybernetics; Mathematical model; Model checking; Protocols; System recovery; Unified modeling language; Use Case Maps; basic protocols; symbolic modeling; verification of requirements;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Requirements Engineering Conference (RE), 2014 IEEE 22nd International
Conference_Location :
Karlskrona
Print_ISBN :
978-1-4799-3031-9
Type :
conf
DOI :
10.1109/RE.2014.6912282
Filename :
6912282
Link To Document :
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