Reduction of the backstage effect in GaAs MESFETS by charge confinement at the backgate electrode

Author

Finchem, E.P. ; Vetanen, W.A. ; Odekirk, B. ; Canfield, P.C.

Author_Institution

TriQuint Semicond. Inc., Beaverton, OR, USA

fYear

1988

fDate

6-9 Nov. 1988

Firstpage

231

Lastpage

234

Abstract

A VLSI-compatible technique for the reduction of the backgate effect in GaAs MESFETs is proposed. The application of this technique to a depletion process has yielded devices with significantly improved low-temperature backgate characteristics and room-temperature backgate thresholds to -35 V, for a 3- mu m backgate/drain spacing. E/D (enhancement/depletion) devices fabricated by this technique reveal no degradation to DC or RF performance while exhibiting backgate thresholds in excess of -6 V and -13 V, respectively. It is concluded that the compatibility of this technique with VLSI GaAs ICs is borne out by the process simplicity, device size, and spacing.<>

Keywords

III-V semiconductors; Schottky gate field effect transistors; VLSI; field effect integrated circuits; integrated circuit technology; 3 micron; DC performance; GaAs; III-V semiconductors; MESFETS; RF performance; VLSI-compatible technique; backgate electrode; backstage effect; charge confinement; depletion process; device size; low-temperature backgate characteristics; room-temperature backgate thresholds; Degradation; Electrodes; Electron traps; Gallium arsenide; Implants; MESFETs; Radio frequency; Temperature; Testing; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1988. Technical Digest 1988., 10th Annual IEEE

Conference_Location

Nashville, Tennessee, USA

Type

conf

DOI

10.1109/GAAS.1988.11064

Filename

11064