Pillar Bump Technology and Integrated Embedded Passive Devices

Author

Jiang, Asen Long Xin ; Ming, Lai Chih ; Gao, Jeff Chen Yi ; Hwee, Tan Kim

Author_Institution

Jiangyin Changdian Adv. Packaging Pte Ltd.

fYear

2006

fDate

26-29 Aug. 2006

Firstpage

1

Lastpage

5

Abstract

In this paper, we will discuss the copper pillar bump structure and comparison will be made with standard solder bump and its advantages. Temperature cycles and high temperature storage reliability on QFN using copper pillar bump were performed. Results show that copper pillar bump can withstand up to 5000 cycles of mechanical stress test without mechanical and electrical failure. Electrical performance was discussed in term of current carrying density and comparison done with standard solder bump and its mean time to failure (MTTF) defined. The pillar bumps show that its MTTF is 2.3 times better than standard bump. JCAP (Jiangyin Changdian Advanced Packaging) uses the copper pillar bump technology and extend the technology to fabricate passive devices onto the chip. This application will improve the electrical performance and also the improve board space utilization

Keywords

electronics packaging; high-temperature electronics; passive networks; solders; MTTF; QFN; copper pillar bump; current carrying density; electrical failure; electrical performance; high temperature storage reliability; integrated embedded passive devices; mechanical failure; mechanical stress test; pillar bump technology; solder bump; Assembly; Bonding forces; Copper; Flip chip; Integrated circuit interconnections; Packaging; Space technology; Temperature; Tin; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Packaging Technology, 2006. ICEPT '06. 7th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0619-6

Electronic_ISBN

1-4244-0620-X

Type

conf

DOI

10.1109/ICEPT.2006.359812

Filename

4198933