DocumentCode :
2577175
Title :
Board Level Drop Test and Simulation of CSP for Handheld Application
Author :
Jiang, Don-Son ; Tzeng, Yuan Lin ; Wang, Yu-Po ; Hsiao, C.S.
Author_Institution :
Siliconware Precision Ind. Co. Ltd., Taichung
fYear :
2006
fDate :
26-29 Aug. 2006
Firstpage :
1
Lastpage :
4
Abstract :
For CSP used in handheld electronic products, such as mobile phone, PDA, etc., the board level drop test has become a great concern, especially in the stage of lead free transition. Comparison between SnPb and lead free Sn4Ag0.5Cu solders, CSP components on board with SnPb solder had much better drop test reliability than lead free one. However, since the drop test is a time-wasting method, the simulation technique is necessary to shorten the design stage and get the optimized solution. In current study, LS-DANA was used to do stress simulation during drop impact. In the beginning, the PCB strain response was compared between modeling and drop test. The result showed good agreement with maximum 15% deviation. The stress in the solder joint was also analyzed and the high stress area in component side was similar with failure mode confirmed by dye and pry analysis after drop test
Keywords :
chip scale packaging; consumer electronics; copper alloys; lead alloys; reliability; silver alloys; solders; stress-strain relations; tin alloys; CSP; SnAgCu; board level drop test; chip scale packaging; drop test reliability; handheld electronic products; solder joints; stress simulation; Capacitive sensors; Design optimization; Electronic equipment testing; Environmentally friendly manufacturing techniques; Failure analysis; Lead; Mobile handsets; Soldering; Stress; Tin;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Packaging Technology, 2006. ICEPT '06. 7th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0619-6
Electronic_ISBN :
1-4244-0620-X
Type :
conf
DOI :
10.1109/ICEPT.2006.359845
Filename :
4198966
Link To Document :
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