Title :
A Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays by Direct Spare Replacement
Author :
Takanami, Itsuo ; Horita, Tadayoshi
Abstract :
We present a self-repairing circuit for a mesh-connected processor array with faulty processing elements which are directly replaced by spare processing elements on two orthogonal lines at the edges of the array. First, the spare assignment problem is formalized as a matching problem in graph theory. Using the result, we present an algorithm for reconstructing the array in a convenient form for finding the matching by a logical circuit. Second, the logical circuit which exactly realizes the algorithm is given. The circuit can be embedded in a target processor array to reconstruct very quickly the array with faulty processing elements without the aid of a host computer. This implies that the proposed system is effective in enhancing especially the run-time reliability of a processor array.
Keywords :
circuit reliability; fault tolerant computing; graph theory; logic devices; built-in circuit; direct spare replacement; faulty processing elements; graph theory; host computer; logical circuit; matching problem; orthogonal lines; run-time reliability; self-repairing mesh-connected processor arrays; spare assignment problem; spare processing elements; Circuit faults; Computers; Graph theory; Hardware; Integrated circuit reliability; Parallel processing; built-in circuit; fault-tolerance; graph theory; mesh array; self-repair;
Conference_Titel :
Dependable Computing (PRDC), 2012 IEEE 18th Pacific Rim International Symposium on
Conference_Location :
Niigata
Print_ISBN :
978-1-4673-4849-2
Electronic_ISBN :
978-0-7695-4885-2
DOI :
10.1109/PRDC.2012.11