DocumentCode :
2577920
Title :
Package-on-Package (PoP) for Advanced PCB Manufacturing Process
Author :
Lee, Joseph Y. ; Ahn, Jinyong ; Yoo, JeGwang ; Kim, Joonsung ; Park, Hwa-Sun ; Okabe, Shuichi
Author_Institution :
Samsung Electro-Mech. Co. Ltd., Gyunggi-Do
fYear :
2006
fDate :
26-29 Aug. 2006
Firstpage :
1
Lastpage :
7
Abstract :
In the 1990´s, both BGA (ball grid array) and CSP (chip size package) are entering their end in the front-end packaging materials and process technology. Both BGA and CSP like SMD (surface mount device) from the 1980´s and THD (through-hole mount device) from the 1970´s are reaching its own impasse in terms of maximizing its electrical, mechanical, and thermal performances, size, weight, and reliability. Now, 3D packages are the next phase for its future use in advanced PCB manufacturing process. They can be classified into wafer level, chip level, and package level stacking. So, package-on-package (PoP), a type of 3D package level stacking, is to be discussed in this paper (Kada et al.)
Keywords :
ball grid arrays; chip scale packaging; manufacturing processes; printed circuit manufacture; surface mount technology; wafer level packaging; 3D packages; 3D-chip-stacked-packaging; advanced PCB manufacturing process; ball grid array; chip level; chip size package; package level stacking; package-on-package; surface mount device; through-hole mount device; wafer level; Assembly; Chip scale packaging; Gold; Manufacturing processes; Packaging machines; Stacking; Thermal stresses; Wafer bonding; Wafer scale integration; Wire; 3D packaging; 3D-chip-stacked-packaging (3D-CSP); folded packages; package-in-package (PiP); package-on-package (PoP); stacked packaging;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Packaging Technology, 2006. ICEPT '06. 7th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0619-6
Electronic_ISBN :
1-4244-0620-X
Type :
conf
DOI :
10.1109/ICEPT.2006.359648
Filename :
4199006
Link To Document :
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