Title :
Chip Parasitic Extraction And Signal Integrity Verification
Author_Institution :
University of California at Santa Cruz
Keywords :
Clocks; Conductors; Delay; Geometry; Logic; Parasitic capacitance; Permission; Solid modeling; Transistors; Wires;
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the 34th
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
0-7803-4093-0
DOI :
10.1109/DAC.1997.597238
