Title :
A low voltage SONOS nonvolatile semiconductor memory technology
Author :
White, Marvin H. ; Yang, Yang ; Purwar, Ansha ; French, Margaret L.
Author_Institution :
Sherman Fairchild Center, Lehigh Univ., Bethlehem, PA, USA
Abstract :
The triple dielectric SONOS (polysilicon-blocking oxide-silicon nitridetunnel oxide-silicon) structure is an attractive candidate for high density E2PROM´s suitable for semiconductor disks and a replacement for high-density DRAMS. Low programming voltages (5 V) and high endurance (greater than 107 cycles) are possible in this multi-dielectric technology as the intermediate Si3N4 layer is scaled to thicknesses of 50 A. The thin gate insulator and low programming voltage enable the scaling of the basic memory cell and as associated CMOS peripheral circuitry on the memory chip. A SONOS 1TC memory cell is proposed in a NOR architecture with a cell area of 6F 2, where F is the technology feature size. A 0.20 μm feature size permits a 1TC area of 0.24 μm2 for advanced 1-Gb nonvolatile semiconductor memory chips. A physical model is presented to characterize the erase/write, retention and endurance properties of the nonvolatile semiconductor memory (NVSM) SONOS device
Keywords :
EPROM; cellular arrays; integrated circuit reliability; integrated memory circuits; semiconductor-insulator-semiconductor devices; CMOS peripheral circuitry; E2PROM; NOR architecture; SONOS; cell area; endurance properties; erase/write; memory chip; multi-dielectric technology; nonvolatile semiconductor memory; programming voltages; retention; semiconductor disks; technology feature size; thin gate insulator; triple dielectric; CMOS memory circuits; CMOS technology; Dielectrics; Insulation; Low voltage; Nonvolatile memory; PROM; Random access memory; SONOS devices; Semiconductor memory;
Conference_Titel :
Nonvolatile Memory Technology Conference, 1996., Sixth Biennial IEEE International
Conference_Location :
Albuquerque, NM
Print_ISBN :
0-7803-3510-4
DOI :
10.1109/NVMT.1996.534669
