DocumentCode
2578395
Title
Multi-interleaved zero-ripple VRM to power future microprocessors
Author
Garinto, Dodi
Author_Institution
Indonesian Power Electron. Center, Surakarta
fYear
2007
fDate
2-5 Sept. 2007
Firstpage
1
Lastpage
8
Abstract
This paper presents a converter architecture derived from the buck topology with merging principle of the multi-interleaving and zero-ripple techniques. The converter not only produces zero-ripple output, but also provides low-ripple input, so that filter requirements in input and output sides can be reduced significantly. The proposed converter shows an ideal solution for future microprocessors.
Keywords
network topology; power convertors; voltage regulators; buck topology; converter architecture; low-ripple input; multi-interleaved zero-ripple VRM; power future microprocessors; voltage regulator modules; zero-ripple output; Filters; Inductors; Interleaved codes; Microprocessors; Power supplies; Switches; Switching frequency; Topology; Transient response; Voltage; Converter circuit; DC power supply; EMC/EMI; Interleaved Converters; Voltage Regulator Modules;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Electronics and Applications, 2007 European Conference on
Conference_Location
Aalborg
Print_ISBN
978-92-75815-10-8
Electronic_ISBN
978-92-75815-10-8
Type
conf
DOI
10.1109/EPE.2007.4417202
Filename
4417202
Link To Document