DocumentCode
2578762
Title
Body-raised double-gate structure for 1T DRAM
Author
Kim, Garam ; Sang Wan Kim ; Song, Jae Young ; Jong Pil Kim ; Ryoo, Kyung-Chang ; Oh, Jeong-Hoon ; Park, Jae Hyun ; Hyun Woo Kim ; Park, Byung-Gook
Author_Institution
Sch. of Electr. Eng., Seoul Nat. Univ., Seoul, South Korea
fYear
2009
fDate
2-5 June 2009
Firstpage
259
Lastpage
263
Abstract
Higher sensing margin and longer retention time are critical issues for commercializing 1T DRAM. In this paper, we propose a body-raised double-gate structure to improve sensing margin and retention time of 1T DRAM and confirm the improvements through 3D simulation. This structure shows about 20% higher sensing margin than the planar structure. We have achieved longer retention time by using high doped raised body and lowering the magnitude of gate bias at hold state.
Keywords
DRAM chips; field effect transistors; silicon-on-insulator; 1T DRAM; SOI; Z-RAM; body-raised double-gate structure; gate bias; high doped raised body; hold state; retention time; sensing margin; Capacitance; Capacitors; Cities and towns; Commercialization; Doping; Impact ionization; Nanotechnology; Random access memory; Semiconductor materials; USA Councils; 1T DRAM; Raised body; SOI; Z-RAM;
fLanguage
English
Publisher
ieee
Conference_Titel
Nanotechnology Materials and Devices Conference, 2009. NMDC '09. IEEE
Conference_Location
Traverse City, MI
Print_ISBN
978-1-4244-4695-7
Electronic_ISBN
978-1-4244-4696-4
Type
conf
DOI
10.1109/NMDC.2009.5167556
Filename
5167556
Link To Document