Parasitic effects induced by power strips current switching in full wafer package

Author

Chilo, J. ; Angenieux, G.

Author_Institution

LEMO, Grenoble, France

fYear

1989

fDate

13-15 June 1989

Firstpage

1259

Abstract

Parasitic effects induced by current switching in power lines for full wafer packages (monolithic or hybrid) are analyzed in the time domain. Theoretical results yield simple relations for easily predicting the dynamic voltage drop on the power line and the parasitic voltages on signal lines induced by coupling with the power line. Experimental measurements on typical devices validate these formulas. The analysis makes it possible to develop optimization criteria for the full wafer interconnect layout or other advanced packages (multichip carriers).<>

Keywords

electrical faults; integrated circuit technology; packaging; switching; time-domain analysis; dynamic voltage drop; full wafer package; hybrid IC; interconnect layout; monolithic IC; multichip carriers; optimization criteria; parasitic effects; parasitic voltages; power line coupling; power strips current switching; signal lines; time-domain analysis; Artificial intelligence; Clocks; Coupling circuits; Frequency; Integrated circuit measurements; Multiprocessor interconnection networks; Packaging; Silicon; Time domain analysis; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest, 1989., IEEE MTT-S International

Conference_Location

Long Beach, CA, USA

Type

conf

DOI

10.1109/MWSYM.1989.38955

Filename

38955