Current-mode CMOS pipelined ADC

CMOS technology scaling trends and power requirements demand circuits which operate at lower supply voltages. However threshold voltage scaling doesn´t exactly follow supply voltage scaling. Therefore circuit techniques like current-mode circuits, which are less sensitive to supply voltage level, are required. In this direction and in the context of mixed-signal design this paper presents two 6-bit pipelined current-mode ADCs in UMC 0.18 um MM (mixed-mode) CMOS process, one for high- speed & low-power and the other for high-resolution applications. Digital error correction has been taken care while designing the ADCs. The maximum sampling rate, average power dissipation and SNR for the first designed ADC, aimed for low-power and high-speed applications are 50 MSPS, 56.38 mW & 36.33 dB, respectively. Similar specifications for another designed ADC, aimed for high-resolution applications, are 16.67 MSPS, 113.5 mW and 38.74 dB, respectively. The ADCs are designed and simulated in UMC 0.18 mum CMOS technology. using Mentor Graphics Custom IC Design tool set.