Design of evolvable hardware using adaptive simulated annealing

Author

Guo-Liang, He ; Yuan-Xiang, Li ; Feng, Liu

Author_Institution

Sch. of Comput., Wuhan Univ., China

Volume

2

fYear

2005

fDate

23-26 Sept. 2005

Firstpage

1390

Lastpage

1392

Abstract

The evolvable hardware technique is based on evolving the functionality and connectivity of a rectangular array of logic cells. In this paper, an adaptive simulated annealing algorithm is proposed for design combinational circuits with 100% functionality and minimized number of gates. Experiments for five combinational circuits with our method are compared with NGA, MGA, MLCEA and human designs produced by Karnaugh maps and Quine-McCluskey method. Results show our method can optimize combinational circuits with shorter chromosome structure and is more adaptive for evolvable hardware.

Keywords

logic circuits; network synthesis; simulated annealing; Karnaugh maps; Quine-McCluskey method; adaptive simulated annealing; combinational circuits; evolvable hardware design; evolvable hardware technique; logic cells; Algorithm design and analysis; Biological cells; Cells (biology); Circuit simulation; Combinational circuits; Computational modeling; Equations; Evolutionary computation; Hardware; Simulated annealing;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Communications, Networking and Mobile Computing, 2005. Proceedings. 2005 International Conference on

Print_ISBN

0-7803-9335-X

Type

conf

DOI

10.1109/WCNM.2005.1544314

Filename

1544314