Unified 3GPP and 3GPP2 turbo encoder FPGA implementation using run-time partial reconfiguration

One key objective of Software Defined radio is to implement multiple standards on common hardware. This can be achieved by partial reconfiguration of Field Programmable Gate Array (FPGA) in which some part of the FPGA remains active while other gets reconfigured. This paper proposes partially reconfigurable design of unified turbo encoder of two 3G standards-3GPP and 3GPP2 on FPGA Xilinx Virtex- IV. The design shows substantial improvement in hardware implementation of the interleavers over the previous designs. In order to achieve the best possible results with partial reconfiguration, maximum common functionality from both the turbo encoders has been identified and a unified architecture has been proposed. Novel ways have been devised to perform the computationally intensive operations of the 3GPP interleaver with minimal hardware requirement and least possible number of clock cycles.