• DocumentCode
    2580869
  • Title

    Accurate RTL power estimation for a security processor

  • Author

    Chang, Kai-Shuang ; Weng, Chia-Chien ; Shi-Yu Huang

  • Author_Institution
    Dept. of Electr. Eng., Nat. Tsing-Hua Univ., HsinChu, Taiwan
  • fYear
    2005
  • fDate
    15-16 Aug. 2005
  • Abstract
    We summarize the experience of estimating the average power dissipation of a security processor (of 430K gates) using an in-house tool, called ToggleFinder. The estimation is done at the register-transfer level (RTL) so that the CPU time can be slashed dramatically. At the same time, the accuracy is retained by two techniques: power mode classification and scalable linear approximation. We found that a security processor containing a number of different encryption and decryption schemes, such as AES and RSA, could consume power very differently from one clock cycle to another. Also, the design gate count of a design block does not reflect how much power it consumes very well. Such a large design demonstrates that our new power estimation method is truly useful in a low-power design process.
  • Keywords
    cryptography; logic design; logic gates; low-power electronics; microprocessor chips; RTL power estimation; ToggleFinder; decryption scheme; design gate count; encryption scheme; low-power design; power dissipation; power mode classification; register-transfer level; scalable linear approximation; security processor; Analytical models; Clocks; Cryptography; Hardware design languages; Linear approximation; National security; Power dissipation; Power generation economics; Process design; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Emerging Information Technology Conference, 2005.
  • Print_ISBN
    0-7803-9328-7
  • Type

    conf

  • DOI
    10.1109/EITC.2005.1544353
  • Filename
    1544353