DocumentCode :
2581145
Title :
A 28GS/s 6b pseudo segmented current steering DAC in 90nm CMOS
Author :
Alpert, Thomas ; Lang, Felix ; Ferenci, Damir ; Grözing, Markus ; Berroth, Manfred
Author_Institution :
Inst. of Electr. & Opt. Commun. Eng., Univ. of Stuttgart, Stuttgart, Germany
fYear :
2011
fDate :
5-10 June 2011
Firstpage :
1
Lastpage :
4
Abstract :
A pseudo segmented twofold time-interleaved 6-bit digital-to-analog converter (DAC) occupies 0.28 mm2 chip area in a standard 90 nm CMOS technology. The DAC enables sampling rates up to 28 GS/s with a power consumption of 2.25 W at a -2.5 V power supply. The output bandwidth is at least 14 GHz. The integral non-linearity (INL) and the differential non-linearity (DNL) are 0.8 LSB and 1 LSB respectively. The estimated effective number of bit (ENOB) at 25 GS/s are 5.5-bit at DC and 4.6-bit at the Nyquist frequency.
Keywords :
CMOS integrated circuits; digital-analogue conversion; CMOS technology; Nyquist frequency; differential nonlinearity; effective number of bit; integral nonlinearity; power 2.25 W; pseudo segmented current steering DAC; size 90 nm; voltage -2.5 V; Bandwidth; CMOS integrated circuits; CMOS technology; Decoding; Layout; Semiconductor device measurement; Synchronization; CMOS; current steering; digital-to-analog converter; pseudo segmentation; time interleaving;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microwave Symposium Digest (MTT), 2011 IEEE MTT-S International
Conference_Location :
Baltimore, MD
ISSN :
0149-645X
Print_ISBN :
978-1-61284-754-2
Electronic_ISBN :
0149-645X
Type :
conf
DOI :
10.1109/MWSYM.2011.5972565
Filename :
5972565
Link To Document :
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