On-chip ΔI noise in the power distribution networks of high speed CMOS integrated circuits

Author

Tang, Kevin T. ; Friedman, Eby G.

Author_Institution

Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA

fYear

2000

fDate

2000

Firstpage

53

Lastpage

57

Abstract

On-chip simultaneous switching noise (SSN) has become an important issue in the design of power distribution networks in current VLSI/ULSI circuits. An analytical expression characterizing the simultaneous switching noise voltage is presented here based on a lumped RLC model. The peak value of the simultaneous switching noise voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak simultaneous switching noise voltage on the circuit behavior

Keywords

CMOS digital integrated circuits; ULSI; VLSI; high-speed integrated circuits; integrated circuit design; integrated circuit modelling; integrated circuit noise; power supply circuits; ULSI circuits; VLSI circuits; circuit-level constraints; design constraints; high speed CMOS ICs; layout-level constraints; lumped RLC model; onchip ΔI noise; onchip simultaneous switching noise; peak SSN voltage; power distribution networks; simultaneous switching noise voltage; very deep submicron circuits; Circuit analysis; Circuit noise; Network-on-a-chip; Power systems; RLC circuits; SPICE; Switching circuits; Ultra large scale integration; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International

Conference_Location

Arlington, VA

Print_ISBN

0-7803-6598-4

Type

conf

DOI

10.1109/ASIC.2000.880675

Filename

880675