A system-level simulation environment for system-on-chip design

This paper presents a mixed-signal/multi-language simulation environment for the languages VHDL-AMS, Java, and C++. The environment is implemented in Java and based upon a previously developed VHDL-AMS design environment consisting of a compiler, an elaborator and a simulator. The latter was extended by open object-oriented Java and C++ interfaces towards system-level simulation capabilities. Obviously, this approach lends itself to a VHDL-centric modeling style. However it also results in a well-defined overall simulation semantics based on the proven semantic principles of VHDL-AMS. Moreover the object-oriented Java and C++ interfaces enforce a much better language modeling style than traditional callback-based procedural language interfaces. The presented open architecture provides good capabilities for research in the field of system-level simulation