Hipar-DSP-a scalable family of high performance DSP-cores

With the HiPAR-DSP family we present a scalable series of high performance fixed point DSPs. The HiPAR-DSP family features up to 16 SIMD controlled datapaths, where each datapath consists of a VLIW controlled set of arithmetic units (16 bit multiply and accumulate, 32 bit ALU and 32 bit shift and round). A shared on-chip memory with specially adapted parallel access is used for communication between the datapaths. The number of datapaths can easily be scaled to adapt the architecture to requirements in terms of processing power and silicon area. A flexible DMA control unit allows easy interfacing for systems on a chip. The maximum configuration of the presented DSP family can sustain a processing power of more than 3 GOPS for actual applications