Optimization of a 0.13 μm CMOS backend interconnect process for ASIC SOC: low K dielectric vs. Cu conductor

A backend optimization scheme for a 0.13 μm CMOS process is illustrated based on a set of performance and process metrics. Performance is measured against manufacturing risk and expense with a focus on the requirements for ASIC/SOC. In evaluating how to effectively optimize 0.13 μm high performance ASIC/SOC, we compared two technology enhancements-Cu and low K. The results demonstrate that low K is comparable in performance with thickness-scaled Cu but with lower manufacturing risk. Further studies show that placing low-k IMD in the top few layers rather than in all the layers provides the most optimal solution for the 0.13 um ASIC/SOC requirements