Title :
Architechture level optimization for asynchronous IPs
Author :
Hardt, W. ; Visarius, M. ; Kleinjohann, B.
Author_Institution :
Dept. of Comput. Sci., Paderborn Univ., Germany
Abstract :
In this paper we present a customized approach to performance and area optimization of asynchronous functional blocks. First an abstract model of the block architecture is introduced and an analytical method for throughput maximization is described. Secondly, area optimization can be performed with respect to data dependencies and merged data paths. These methods have been implemented and validated by several examples. A first chip implementing all relevant architecture blocks has been produced. The chip is named FLYSIG and operates completely delay-insensitive
Keywords :
circuit optimisation; data flow graphs; embedded systems; industrial property; integrated circuit design; logic CAD; pipeline processing; FLYSIG; abstract model; architecture level optimization; area optimization; asynchronous IPs; data dependencies; delay-insensitive operation; functional blocks; merged data paths; performance optimization; throughput maximization; Computer architecture; Costs; Delay; Embedded system; Energy consumption; Performance analysis; Power system modeling; Process design; Quantization; Throughput;
Conference_Titel :
ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6598-4
DOI :
10.1109/ASIC.2000.880694
