DocumentCode :
2581896
Title :
Physical planning of on-chip interconnect architectures
Author :
Chen, Hongyu ; Yao, Bo ; Zhou, Feng ; Cheng, Chung-Kuan
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of California, La Jolla, CA, USA
fYear :
2002
fDate :
2002
Firstpage :
30
Lastpage :
35
Abstract :
Interconnect architecture plays an important role in determining the throughput of meshed communication structures. We assume a mesh structure with uniform communication demand for communication. A multi-commodity flow (MCF) model is proposed to find the throughput for several different routing architectures. The experimental results reveal several trends: 1. The throughput is limited by the capacity of the middle row and column in the mesh, simply enlarging the congested channel cannot produce better throughput. A flexible chip shape provides around 30% throughput improvement over a square chip of equal area. 2. A 45-degree mesh allows 17% throughput improvement over 90-degree mesh and a 90-degree and 45-degree mixed mesh provides 30% throughput improvement. 3. To achieve maximum throughput on a mixed Manhattan and diagonal interconnect architecture, the best ratio of the capacity for diagonal routing layers and the capacity for Manhattan routing layers is 5.6. 4. Incorporating a simplified via model, interleaving diagonal routing layers and Manhattan routing layer is the best way to organize the wiring directions on different layers.
Keywords :
circuit layout CAD; system-on-chip; congested channel; diagonal interconnect architecture; flexible chip shape; mesh structure; meshed communication structures; mixed Manhattan interconnect architecture; multi-commodity flow model; on-chip interconnect architectures; physical planning; throughput; via model; Channel capacity; Communication networks; Computer architecture; Field programmable gate arrays; Integrated circuit interconnections; Routing; Telecommunication traffic; Throughput; Traffic control; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on
ISSN :
1063-6404
Print_ISBN :
0-7695-1700-5
Type :
conf
DOI :
10.1109/ICCD.2002.1106743
Filename :
1106743
Link To Document :
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