Using computational RAM for volume rendering

Author

Snip, Anco K. ; Elliott, Duncan G. ; Margala, Martin ; Durdle, Nelson G.

Author_Institution

Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada

fYear

2000

fDate

2000

Firstpage

253

Lastpage

257

Abstract

The gap between processor speed and memory access time limits the performance of memory-intensive applications such as volume rendering. In this paper we compare the performance of stages of the splatting volume rendering algorithm on a workstation and on the Computational RAM (C·RAM) simulator. C·RAM is a Processor-in-Memory architecture, which integrates SIMD processing elements into the memory array. These processing elements exploit the highest bandwidth available in the memory chip-at the sense amplifiers. Each stage executes faster on C·RAM

Keywords

VLSI; application specific integrated circuits; computer graphic equipment; memory architecture; microprocessor chips; parallel architectures; random-access storage; rendering (computer graphics); ASIC; C·RAM simulator; SIMD processing elements; SoC strategy; computational RAM; memory array; memory-intensive application; processor-in-memory architecture; splatting volume rendering algorithm; system-on-a-chip strategy; volume rendering; Application specific integrated circuits; Bandwidth; Built-in self-test; Computer architecture; Hardware; Pipelines; Random access memory; Read-write memory; System-on-a-chip; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International

Conference_Location

Arlington, VA

Print_ISBN

0-7803-6598-4

Type

conf

DOI

10.1109/ASIC.2000.880711

Filename

880711