Title :
A complete model for glitch analysis in logic circuits
Author :
Chung, Ki-Seok ; Kim, Taewhan ; Liu, C.L.
Author_Institution :
Synopsys Inc., Mountain View, CA, USA
Abstract :
One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many such switching activities are due to spurious pulses, called glitches. Recently, a new model of glitch analysis, called G-vector has been proposed. The power of the model is that, unlike the existing ones which model only the propagation of glitches to count the number of glitches in the circuits, it allows one to model the generation, propagation and elimination of glitches to be able to not only count the number of glitches but also locate the glitches. In this paper, we complete the concept of G-vector by providing a set of efficient solutions to the two important practical issues: (1) extending to signals over multiple clock cycles, and (2) extending to a logic decomposition utilizing the model. Integrating the solutions all together enables G-vector to be very efficient. A set of experimental results is provided to show the effectiveness of the proposed solutions
Keywords :
CMOS logic circuits; clocks; combinational circuits; integrated circuit modelling; logic CAD; low-power electronics; CMOS combinational logic circuits; G-vector; glitch analysis model; logic decomposition; multiple clock cycles; power consumption; spurious pulses; switching activities; CMOS logic circuits; Circuit analysis; Circuit synthesis; Clocks; Combinational circuits; Energy consumption; Logic circuits; Power dissipation; Semiconductor device modeling; Switching circuits;
Conference_Titel :
ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6598-4
DOI :
10.1109/ASIC.2000.880714
