Title :
High level functional verification closure
Author :
Dudani, Surrendra ; Nagda, Jayant
Abstract :
We present a methodology to obtain high level functional verification closure. We discuss the current advances in critical technologies that are part of the verification closure solution. Within this methodology, assertion specifications are the starting point and central to the collaboration required between various verification tasks to efficiently search for tests and allow automation to proceed. The goal of verification closure is to generate a complete set of tests that meet the design quality criteria established for the design.
Keywords :
automation; computer testing; electronic design automation; formal verification; assertion specifications; automation; design quality criteria; high level functional verification closure; tests; Automatic testing; Collaboration; Computer bugs; Electronic design automation and methodology; Hardware design languages; Monitoring; Process design; Runtime; Signal design; System testing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on
Print_ISBN :
0-7695-1700-5
DOI :
10.1109/ICCD.2002.1106753