Title :
An extended class of sequential circuits with combinational test generation complexity
Author :
Inoue, Michiko ; Jinno, Chikateru ; Fujiwara, Hideo
Author_Institution :
Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
Abstract :
We introduce a class of sequential circuits with internally switched balanced structure which allows test generation with combinational test generation complexity. The proposed class includes any other known classes with this feature. This paper also considers faults in hold registers and switches regarded as macros, while any related work does not consider faults in such macros. Experimental results show the effectiveness of using combinational test generation for the circuits with internally switched balanced structure.
Keywords :
automatic test pattern generation; circuit complexity; sequential circuits; combinational test generation complexity; complexity; full scan design; internally switched balanced structure; sequential circuits; test generation; Circuit faults; Circuit testing; Combinational circuits; Flip-flops; Information science; Registers; Sequential analysis; Sequential circuits; Switches; Switching circuits;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on
Print_ISBN :
0-7695-1700-5
DOI :
10.1109/ICCD.2002.1106770
