DocumentCode
2582569
Title
Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits
Author
Ker, Ming-Dou ; Jiang, Hsin-Chin ; Chang, Chyh-Yih
Author_Institution
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
2000
fDate
2000
Firstpage
293
Lastpage
296
Abstract
A new structure of bond pad is proposed to reduce its parasitic capacitance in a baseline CMOS process without any process modification. The proposed bond pad has a capacitance less than 50% of that in the traditional bond pad. In addition, this new bond pad also provides better bonding adhesion of 10% improvement than the traditional one. It is very useful for high-frequency IC´s, which need a very low input capacitance
Keywords
CMOS integrated circuits; UHF integrated circuits; adhesion; capacitance; high-speed integrated circuits; integrated circuit layout; integrated circuit metallisation; CMOS ICs; ESD protection; HF I/O applications; baseline CMOS process; bonding adhesion; high-frequency ICs; input capacitance; low-capacitance bond pad design; parasitic capacitance reduction; Adhesives; Atherosclerosis; Bonding; CMOS integrated circuits; CMOS process; CMOS technology; Electrostatic discharge; Parasitic capacitance; Protection; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International
Conference_Location
Arlington, VA
Print_ISBN
0-7803-6598-4
Type
conf
DOI
10.1109/ASIC.2000.880752
Filename
880752
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