Title :
Power optimization of delay constrained circuits
Author :
Nayak, Anshuman ; Haldar, Malay ; Banerjee, Prith ; Chen, Chunhong ; Sarrafzadeh, Majad
Author_Institution :
Centre for Parallel & Distributed Comput., Northwestern Univ., Evanston, IL, USA
Abstract :
We present a framework for combining Voltage Scaling (VS) and Gate Sizing (GS) techniques for power optimizations. We introduce a fast algorithm for choosing gates for sizing and voltage scaling such that the total power is minimized under delay constraints. We also use a more accurate estimate for determining the power dissipation of the circuit by taking into account the short circuit power along with the dynamic power. A better model of the short circuit power is used which takes into account the loading capacitance of the gates. Our results show that the combination of VS and GS perform better than the techniques applied in isolation. An average power reduction of 73% is obtained when decisions are taken assuming dynamic power only. In contrast, average power reduction is 77% when decisions include the short circuit power dissipation
Keywords :
CMOS digital integrated circuits; VLSI; capacitance; circuit CAD; circuit layout CAD; circuit optimisation; delays; high level synthesis; integrated circuit design; low-power electronics; timing; delay constrained circuits; dynamic power dissipation; fast algorithm; gate sizing techniques; loading capacitance; power dissipation estimation; power model; power optimization; power reduction; short circuit power dissipation; timing model; total power minimization; voltage scaling techniques; CMOS logic circuits; Capacitance; Constraint optimization; Delay effects; Distributed computing; Isolation technology; Portable computers; Power dissipation; Threshold voltage; Transistors;
Conference_Titel :
ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6598-4
DOI :
10.1109/ASIC.2000.880754
