Low-power skewed static logic (S2L) with topology-dependent dual Vt

In this paper, we describe Skewed Static Logic (S²L) with topology-dependent dual Vt which exhibits low-power, high-performance operation. S²L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. The noise tolerance of proposed technique is presented with simulation results. We have designed NAND-NOR gate chains using 0.18 μm CMOS technology and verified that S²L reduces energy×delay over MS CMOS by 27-50%. We have also designed 32-bit carry-lookahead adders and verified that S²L with dual Vt reduces delay by 43% and energy×delay by 31% over the conventional CMOS circuit for 1 V power supply