Title :
Power optimization of standard cell flip flops
Author :
Rasmussen, Bryce ; Wright, John A.
Author_Institution :
American Microsystems Inc., Pocatello, ID, USA
Abstract :
Flip-flops are not normally considered when the analysis of chip power is made for a deep-submicron circuit. When the gate counts get above 250,000, the flip-flop and associated clock trees then become the major source of power consumption on the chip, exceeding the power consumption of even the hundreds of outputs. Innovations and trade-offs are discussed in this paper that reduce the power in the flip-flops and associated clock trees by up to 60% while slightly improving the performance over standard flip-flop configurations
Keywords :
VLSI; circuit feedback; circuit optimisation; digital integrated circuits; flip-flops; low-power electronics; chip power; clock trees; deep-submicron circuit; power consumption reduction; power optimization; standard cell flip flops; Capacitance; Circuit simulation; Circuit testing; Clocks; Energy consumption; Flip-flops; Power dissipation; Silicon; Switches; Threshold voltage;
Conference_Titel :
ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6598-4
DOI :
10.1109/ASIC.2000.880756
