Power optimization of standard cell flip flops

Flip-flops are not normally considered when the analysis of chip power is made for a deep-submicron circuit. When the gate counts get above 250,000, the flip-flop and associated clock trees then become the major source of power consumption on the chip, exceeding the power consumption of even the hundreds of outputs. Innovations and trade-offs are discussed in this paper that reduce the power in the flip-flops and associated clock trees by up to 60% while slightly improving the performance over standard flip-flop configurations