DocumentCode :
2582643
Title :
The Imagine Stream Processor
Author :
Kapasi, Ujval J. ; Dally, William J. ; Rixner, Scott ; Owens, John D. ; Khailany, Brucek
Author_Institution :
Comput. Syst. Lab., Stanford Univ., CA, USA
fYear :
2002
fDate :
2002
Firstpage :
282
Lastpage :
288
Abstract :
The Imagine Stream Processor is a single-chip programmable media processor with 48 parallel ALUs. At 400 MHz, this translates to a peak arithmetic rate of 16 GFLOPS on single-precision data and 32 GOPS on 16 bit fixed-point data. The scalability of Imagine´s programming model and architecture enable it to achieve such high arithmetic rates. Imagine executes applications that have been mapped to the stream programming model. The stream model decomposes applications into a set of computation kernels that operate on data streams. This mapping exposes the inherent locality and parallelism in the application, and Imagine exploits the locality and parallelism to provide a scalable architecture that supports 48 ALUs on a single chip. This paper presents the Imagine architecture and programming model in the first half and explores the scalability of the Imagine architecture in the second half.
Keywords :
digital arithmetic; digital signal processing chips; parallel architectures; reconfigurable architectures; 16 GFLOPS; 400 MHz; Imagine Stream Processor; computation kernels; fixed-point data; locality; parallel ALUs; parallelism; peak arithmetic rate; programming model; scalability; scalable architecture; single-chip programmable media processor; single-precision data; stream programming model; Arithmetic; Bandwidth; Computer architecture; Concurrent computing; Kernel; Laboratories; Parallel processing; Prototypes; Scalability; Streaming media;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on
ISSN :
1063-6404
Print_ISBN :
0-7695-1700-5
Type :
conf
DOI :
10.1109/ICCD.2002.1106783
Filename :
1106783
Link To Document :
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