A differential high-speed digital CMOS buffer with hysteresis for improved noise immunity

A digital CMOS buffer circuit with a voltage transfer characteristic (VTC) with low threshold voltages, hysteresis, and high noise immunity is presented. The circuit is capable of restoring slow transition times and distorted input signals with a minimum delay penalty, offering high noise immunity to glitches induced either through capacitive coupling or from the power supply lines such as simultaneous switching noise (SSN). The high noise immunity of the proposed buffer circuit is achieved using a differential redundant circuit architecture