Efficient static timing analysis in presence of crosstalk

Author

Tong Xiao ; Chih-Wei Chang ; Marek-Sadowska, M.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA

fYear

2000

fDate

13-16 Sept. 2000

Firstpage

335

Lastpage

339

Abstract

In this paper we show that iterative updating of timing windows is necessary when signals on the same path are mutually capacitively coupled. To improve the accuracy of timing analysis we use implications induced by functional irredundant path sensitization criteria. Experimental results have demonstrated the efficacy and efficiency of our proposed techniques.

Keywords

crosstalk; delays; fault diagnosis; integrated circuit testing; iterative methods; logic testing; timing; IC testing; crosstalk; delay fault testing; functional irredundant path sensitization criteria; iterative updating; mutually capacitively coupled signals; static timing analysis; timing windows; Coupling circuits; Crosstalk; Delay estimation; Integrated circuit interconnections; Signal analysis; Signal processing; Switches; Switching circuits; Timing; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International

Conference_Location

Arlington, VA, USA

Print_ISBN

0-7803-6598-4

Type

conf

DOI

10.1109/ASIC.2000.880760

Filename

880760

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2582721