Title :
A zero-overhead self-timed divider using new pipeline scheme
Author :
Yang, Jing-ling ; Choy, Chiu-Sing ; Chan, Cheong-Fat
Author_Institution :
Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, China
Abstract :
This paper investigates the potential self-timed property of DCVSL circuits, and examines architecture techniques for providing self-timing in DCVSL circuits. As a result a new self-timed technique combined with high-speed dual-rail dynamic circuits is verified using a custom self-timed mantissa divider
Keywords :
asynchronous circuits; cellular arrays; dividing circuits; pipeline arithmetic; DCVSL circuits; high-speed dual-rail dynamic circuits; mantissa divider; pipeline scheme; zero-overhead self-timed divider; Circuits; Clocks; Computer architecture; Delay; Logic; Pipelines; Protocols; Rails; Signal generators; Throughput;
Conference_Titel :
ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6598-4
DOI :
10.1109/ASIC.2000.880765
