DocumentCode :
2582993
Title :
BlockChop: Dynamic squash elimination for hybrid processor architecture
Author :
Mars, Jason ; Kumar, Naveen
Author_Institution :
Univ. of Virginia, Charlottesville, VA, USA
fYear :
2012
fDate :
9-13 June 2012
Firstpage :
536
Lastpage :
547
Abstract :
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative optimization. As we move to a multicore hybrid design, fine grained conflicts for shared data can violate the atomicity requirement of these blocks and lead to expensive squashes and rollbacks. However, as these atomic regions differ from those used in checkpointing and transactional memory systems, the extent of this potentially prohibitive problem remains unclear, and mechanisms to mitigate these squashes dynamically may be critical to enable a highly performant multicore hybrid design. In this work, we investigate how multithreaded applications, both benchmark and commercial workloads, are affected by squashes, and present dynamic mechanisms for mitigating these squashes in hybrid processors. While the current wisdom is that there is not a significant number of squashes for smaller atomic regions, we observe this is not the case for many multithreaded workloads. With region sizes of just 200 - 500 instructions, we observe a performance degradation ranging from 10% to more than 50% for workloads with a mixture of shared reads and writes. By harnessing the unique flexibility provided by the software subsystem of hybrid processor design, we present BlockChop, a framework for dynamically mitigating squashes on multicore hybrid processors. We present a range of squash handling mechanisms leveraging retrials, interpretation, and retranslation, and find that BlockChop is quite effective. Over the current response to exceptions and squashes in a hybrid design, we are able to improve the performance of benchmark and commercial workloads by 1.4x and 1.2x on average for large and small region sizes respectively.
Keywords :
checkpointing; concurrency control; hardware-software codesign; multi-threading; multiprocessing systems; optimisation; BlockChop; HW/SW co-designed processors; aggressive speculative optimization; atomic blocks; checkpointing; dynamic squash elimination; hybrid processor architecture; multicore hybrid design; multithreaded applications; performance degradation; software subsystem; squash handling mechanisms; transactional memory systems; Benchmark testing; Hardware; Multicore processing; Optimization; Registers; Software;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Architecture (ISCA), 2012 39th Annual International Symposium on
Conference_Location :
Portland, OR
ISSN :
1063-6897
Print_ISBN :
978-1-4673-0475-7
Electronic_ISBN :
1063-6897
Type :
conf
DOI :
10.1109/ISCA.2012.6237046
Filename :
6237046
Link To Document :
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