DocumentCode :
2583018
Title :
Accelerated SAT-based scheduling of control/data flow graphs
Author :
Memik, Seda Ogrenci ; Fallah, Farzan
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
fYear :
2002
fDate :
2002
Firstpage :
395
Lastpage :
400
Abstract :
In this paper we present a satisfiability-based approach to the scheduling problem in high-level synthesis. We formulate the resource constrained scheduling as a satisfiability (SAT) problem. We present experimental results on the performance of the state-of-the-art SAT solver Chaff, and demonstrate techniques to reduce the SAT problem size by applying bounding techniques on the scheduling problem. In addition, we demonstrate the use of transformations on control data flow graphs such that the same lower bound techniques can operate on them as well. Our experiments show that Chaff is able to outperform the integer linear program (ILP) solver CPLEX in terms of CPU time by as much as 59 fold. Finally, we conclude that the satisfiability-based approach is a promising alternative for obtaining optimal solutions to NP-complete scheduling problem instances.
Keywords :
computability; computational complexity; data flow graphs; high level synthesis; processor scheduling; CPU time; Chaff; NP-complete scheduling problems; accelerated SAT-based scheduling; bounding techniques; control data flow graphs; high-level synthesis; optimal solutions; resource constrained scheduling; satisfiability-based approach; Acceleration; Binary decision diagrams; Boolean functions; Computer science; Data structures; Flow graphs; High level synthesis; Logic testing; Processor scheduling; Upper bound;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on
ISSN :
1063-6404
Print_ISBN :
0-7695-1700-5
Type :
conf
DOI :
10.1109/ICCD.2002.1106801
Filename :
1106801
Link To Document :
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