Concurrent error detection of polynomial basis multiplication over extension fields using a multiple-bit parity scheme

Cryptographic systems implemented using VLSI technologies require a large number of circuits and are prone to faults. Attacks on cryptosystems that exploit erroneous results due to faults in hardware have recently been reported in the literature. As a result, the detection and correction of errors in cryptographic operations have become an important issue. This paper discusses the detection of multiple-bit faults in bit-serial and bit-parallel polynomial basis multipliers over binary extension fields. Our approach is based on multiple-bit parity. Results show that due to an increase in the number of parity bits, area overhead increases linearly, but the probability of error detection approaches unity sharply so that it reaches 0.95 for 6 parity bits.