A self checking Reed Solomon encoder: design and analysis

Author

Cardarilli, G.C. ; Pontarelli, S. ; Re, M. ; Salsano, A.

Author_Institution

Dept. of Electron. Eng., Univ. of Rome "Tor Vergata", Italy

fYear

2005

fDate

3-5 Oct. 2005

Firstpage

111

Lastpage

119

Abstract

Reed Solomon codes are widely used to identify and correct data errors in transmission and storage systems. Due to the vital importance of these blocks, a very important research topic is the study of the effects of faults on their behavior. The presented architecture exploits some properties of the arithmetic operations on GF(2ⁿ) Galois field, related to the parity of the binary representation of the elements of the field. The encoder has been mapped on an SRAM based FPGA, the self-checking property has been analyzed using a SEU fault model and the performances in terms of area and delay overhead are presented.

Keywords

Galois fields; Reed-Solomon codes; SRAM chips; digital arithmetic; error correction codes; fault diagnosis; field programmable gate arrays; GF(2ⁿ) Galois field; Reed Solomon codes; SEU fault model; SRAM based FPGA device; arithmetic operations; binary representation; data error correction; self checking Reed Solomon encoder; Arithmetic; Circuit faults; Data engineering; Decoding; Encoding; Error correction codes; Galois fields; Protection; Reed-Solomon codes; Single event upset;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2005. DFT 2005. 20th IEEE International Symposium on

ISSN

1550-5774

Print_ISBN

0-7695-2464-8

Type

conf

DOI

10.1109/DFTVS.2005.13

Filename

1544509