DocumentCode
2583970
Title
Methodologies and algorithms for testing switch-based NoC interconnects
Author
Grecu, Cristian ; Pande, Partha ; Wang, Baosheng ; Ivanov, André ; Saleh, Res
Author_Institution
Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada
fYear
2005
fDate
3-5 Oct. 2005
Firstpage
238
Lastpage
246
Abstract
In this paper, we present two novel methodologies for testing the interconnect fabrics of network-on-chip (NoC) based chips. Both use the concept of recursive testing, with different degrees of parallelism in each case. Our test methodologies cover the logic switching blocks and the FIFO buffers that are the basic components of NoC fabrics. The paper concludes with test time evaluations for different NoC topologies and sizes.
Keywords
buffer circuits; integrated circuit interconnections; integrated circuit testing; logic circuits; logic testing; network-on-chip; FIFO buffers; NoC interconnect testing; NoC topology; integrated circuit testing; logic switching blocks; network-on-chip; recursive testing; switched based NoC interconnects; Communication switching; Computer architecture; Fabrics; Logic testing; Network topology; Network-on-a-chip; Parallel processing; Switches; Technology management; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2005. DFT 2005. 20th IEEE International Symposium on
ISSN
1550-5774
Print_ISBN
0-7695-2464-8
Type
conf
DOI
10.1109/DFTVS.2005.45
Filename
1544522
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