Title :
A technique for modular design of self-checking carry-select adder
Author :
Vasudevan, D.P. ; Lala, P.K.
Author_Institution :
Dept. of Comput. Sci. & Comput. Eng., Arkansas Univ., Fayetteville, AR, USA
Abstract :
The carry-select adders provide significant speed improvement over other types of adders. This paper proposes a new approach for constructing self-checking carry-select adders set of faults online. Adders of arbitrary size can be constructed by simply cascading the appropriate number of 2-bit adders. A range of adders from 4 bit to 128 bits was designed using this approach employing a 0.5μm CMOS technology. The area needed for implementing the self-checking adders is 16.07 % to 20.67% more than that required in adders without built-in self-checking capability.
Keywords :
CMOS logic circuits; adders; carry logic; fault diagnosis; integrated circuit design; logic design; 0.5 micron; 2 bit; 4 to 128 bit; CMOS technology; modular design; online fault detection; self-checking carry-select adders; Adders; Arithmetic; CMOS technology; Circuit faults; Computer science; Electrical fault detection; Fault detection; Multiplexing; Testing; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2005. DFT 2005. 20th IEEE International Symposium on
Print_ISBN :
0-7695-2464-8
DOI :
10.1109/DFTVS.2005.15