Simulating faults of combinational IP core-based SOCs in a PLI environment

This paper presents a new test methodology which utilizes the programming language interface (PLI) for performing fault simulation of combinational or full scan intellectual property (IP) core-based designs for system-on-chip (SOC). Using the latest Verilog PLI, referred to as Verilog procedural interface (VPI), critical-path tracing and two-value deductive fault simulations are performed on a pre-compiled core basis as available in a simulator´s intermediate format. By applying this VPI-based test methodology on ISCA S85 Verilog benchmarks results are presented in terms of elapsed simulation time and fault coverage for stuck-at faults and improvement over previous works is reported.