DocumentCode
2584546
Title
Improving thermal-safe test scheduling for core-based systems-on-chip using shift frequency scaling
Author
Tafaj, Enkelejda ; Rosinger, Paul ; Al-Hashimi, Bashir M. ; Chakrabarty, Krishnendu
Author_Institution
Sch. of Electron. & Comput. Sci., Southampton Univ., UK
fYear
2005
fDate
3-5 Oct. 2005
Firstpage
544
Lastpage
551
Abstract
Recently, we have shown how hot-spots during test can be avoided without unnecessarily increasing the testing time by using a thermal-safe test scheduling approach (Rosinger and Al-Hashimi, 2005). In this work, we investigate the impact of scan shift frequency scaling on the thermal-safe test scheduling performance and propose an algorithm which embeds shift frequency scaling into the test scheduling process. Experimental results show that this approach offers shorter overall testing times and significantly improved ability of meeting tight thermal constraints when compared to existing thermal-safe test scheduling approach based on a fixed scan shift frequency.
Keywords
integrated circuit testing; safety; scheduling; system-on-chip; core-based systems-on-chip; fixed scan shift frequency; shift frequency scaling; thermal constraints; thermal-safe test scheduling; Electronic equipment testing; Energy consumption; Frequency; Job shop scheduling; Processor scheduling; Scheduling algorithm; Switches; System testing; Temperature; Thermal stresses;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2005. DFT 2005. 20th IEEE International Symposium on
ISSN
1550-5774
Print_ISBN
0-7695-2464-8
Type
conf
DOI
10.1109/DFTVS.2005.40
Filename
1544554
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