Design of a CMOS operational amplifier amenable to extreme voltage stress

Author

Quan, Shaolei ; Liu, Meng-Yao ; Wey, Chin-Long

Author_Institution

Michigan State Univ., East Lansing, MI, USA

fYear

2005

fDate

3-5 Oct. 2005

Firstpage

563

Lastpage

572

Abstract

Extreme voltage stress (EVS) is an attractive burn-in technique employed in production test to weed out weak chips that may cause infant mortality. Application of this technique to analog integrated circuit (IC) has, however, only achieved limited success due to the significant irregularity in circuit topology. This paper examines the issue of design for EVS in analog IC and presents several analog circuit structures use of which enhances voltage stressability of analog circuits. Based on proposed circuit concepts an operational amplifier is designed in TSMC 0.18μm CMOS technology and is simulated with HSPICE. Simulation results have shown that the designed operational amplifier is fully stressable with slight performance degradation.

Keywords

CMOS analogue integrated circuits; integrated circuit design; operational amplifiers; 0.18 micron; CMOS operational amplifiers; analog circuit structures; analog integrated circuits; circuit topology; extreme voltage stress; voltage stress enhancement; Analog circuits; Analog integrated circuits; Application specific integrated circuits; CMOS technology; Circuit simulation; Circuit testing; Operational amplifiers; Production; Stress; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2005. DFT 2005. 20th IEEE International Symposium on

ISSN

1550-5774

Print_ISBN

0-7695-2464-8

Type

conf

DOI

10.1109/DFTVS.2005.31

Filename

1544556