DocumentCode :
2584575
Title :
Design of sub-10-picoseconds on-chip time measurement circuit
Author :
Abas, M.A. ; Russell, G. ; Kinniment, D.J.
Author_Institution :
Dept. of Electr. & Electron. Eng., Newcastle upon Tyne Univ., UK
Volume :
2
fYear :
2004
fDate :
16-20 Feb. 2004
Firstpage :
804
Abstract :
The rapid pace of change in IC technology, specifically in speed of operation, demands sophisticated design solutions for IC testing methodologies. Moreover, the current technology of system-on-chip (SOC) makes great demands for testing internal speed accurately as the limitation on accessing internal nodes using I/O pins becomes more difficult. This paper presents two high-resolution time measurement schemes for digital BIST applications, namely: two-delay interpolation method (TDIM) and time amplifier. The two schemes are combined to produce a completely new design for BIST time measurement which offers two main advantages: a low range of timing measurement which has never been achieved before, and a small size of layout occupying 0.2 mm2 or equivalent to 3020 transistors. These two features are undoubtedly compatible with present high-speed SOC design architectures.
Keywords :
built-in self test; digital integrated circuits; integrated circuit design; integrated circuit testing; system-on-chip; time measurement; I/O pins; IC testing; SOC; built in self test; digital BIST; input/output pins; integrated circuit testing; internal nodes; internal speed testing; on-chip time measurement circuit design; system-on-chip; time amplifier; two delay interpolation method; Built-in self-test; Circuit testing; Integrated circuit testing; Interpolation; Pins; Size measurement; System testing; System-on-a-chip; Time measurement; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
ISSN :
1530-1591
Print_ISBN :
0-7695-2085-5
Type :
conf
DOI :
10.1109/DATE.2004.1268980
Filename :
1268980
Link To Document :
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