Timing scheme of floating-point based digital controller for DC-DC Converters

This paper mainly proposes a timing scheme of a digitally controlled DC-DC converter, which is described in hardware description language (HDL) at the functional level. FPGA is adopted for the optimization of computation, sampling and modulation to get precise and fast dynamic response of DC-DC converters. The concept of this timing scheme is broad and includes DPWM scheme, sampling scheme and computation scheme. Computational accuracy of the scheme is guaranteed by floating-point arithmetic. At the same time, fast integer-float and float-integer converters are developed based on look-up tables and real-time computation which can greatly reduce the duty pulse width computation clock cycles. A specific sampling and PWM scheme are designed to eliminate compensator delay caused by sampling and hold and the computation process. High precision digital pulse-width modulator based on second-order sigma-delta concept (Σ-ΔDPWM) and dual-mode compensator method are implemented to eliminate steady Limit-Cycle and to maintain fast dynamic response as well. This design is made for IC design verification to practically used digital DC-DC converters.