A power-efficient real-time architecture for SURF feature extraction

This paper presents a novel FPGA-based architecture for the Speeded-Up Robust Feature (SURF) extractor. By leveraging the inherent parallelism of the SURF algorithm, we designed a fully pipelined architecture implemented on the FPGA fabric of a Xilinx Zynq-7020 device (XC7Z020CLG484-1). Compared with other high-performing SURF designs in the literature, our implementation achieved the highest frame rate (131.36 fps) while compactly fitting on a single device and consuming only 0.608 Watts of average power. An experimental platform featuring a 640×480 resolution camera was used to compare the proposed design with OpenSURF, a widely used open-source C++ library, running on a high-end Intel i7 processor. Our system achieved real-time performance independent of the number of interest points extracted from the targeted image, and consistently outperformed the SURF software baseline, reaching a maximum speedup of 15. An extensive analysis was conducted to prove that the performance of our proposed architecture was as robust as the SURF algorithm to image transformations (rotation and scaling) and image distortions (blurring and pixelation), demonstrating that interest-point repeatability was maintained under varying viewing conditions.