Efficient FPGA-based implementation of a CAZAC sequence generator for 3GPP LTE

This paper presents a configurable and optimized hardware architecture for computing Zadoff-Chu (ZC) complex sequences in the frequency domain. It is a hardware-efficient and accurate architecture for computing ZC sequences in realtime. The architecture is mainly based on the CORDIC algorithm for computing complex exponentials using only shift and add operations. Due to transformations applied to the Zadoff-Chu equation it is possible to eliminate the use of multipliers with non-constant terms. This hardware architecture is employed by the Physical Random Access Channel (PRACH) in LTE and LTE-A systems during the reception and detection of random access preambles. Its main advantage is that it eliminates the need for storing a large number of long complex ZC sequences. Simulation results show that the proposed architecture is accurate, efficient and renders the resulting PRACH receiver fully compliant with 3GPP´s detection requirements.