R-1 Merged Logic And DRAM

Summary form only given. We will discuss the types of application that may be suitable for merged DRAM and logic integrated circuits. Further we will pose the challenge of how these products can be tested within the constraints already imposed by pure logic and DRAM implementations. For example, is a two pass test procedure going to be acceptable or will on-chip logic be dedicated to testing of the DRAM? Further we will explore how each application lends itself to the implementation of redundancy to maximize yield.